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HANBit
HSD32M32M4V
Synchronous DRAM Module 128Mbyte ( 32M x 32-Bit ) 72-Pin SIMM based on 32Mx8, 4Banks, 8K Ref., 3.3V Part No. HSD32M32M4V
GENERAL DESCRIPTION
The HSD32M32M4V is a 32M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages mounted on a 72-pin, FR-4-printed circuit board. Two 0.01uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The HSD32M32M4V is a SIMM designed. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* Part Identification HSD32M32M4V-13/F13 :133MHz ( CL=3) HSD32M32M4V-12/F12: 125MHz (CL=3) HSD32M32M4V-10/F10: 100MHz (CL=2) HSD32M32M4V-10L/F10L: 100MHz F means Auto & Self refresh with Low - Power (3.3V) * Burst mode operation * Auto & self refresh capability (8192 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * FR4-PCB design * 72-Pin SIMM Package * The used device is 8Mx8bitx4Bank SRAM * Pin assignment is compatible with - HSD8M32M4V - HSD16M32M4V PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PIN ASSIGNMENT
SYMBOL Vss DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM0 Vcc NC A0 A1 A2 A3 A4 Vss DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL DQ14 DQ15 DQM1 NC /WE /CAS Vcc /RAS /CS0 NC NC CLK0 CKE0 Vss DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM2 Vcc PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL A5 A6 A7 A8 A9 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM3 NC A10/AP A11 A12 Vcc BA0 BA1 NC NC Vss
72-PIN SIMM TOP VIEW
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FUNCTIONAL BLOCK DIAGRAM
HSD32M32M4V
DQ0-31
CKE0 /CAS /RAS /CE1
CKE CAS RAS CE WE A0-A12
CLK
CLK0
U1
DQ0-7 DQM0 BA0-1 DQM0
CKE CAS RAS CE WE A0-A12
CLK
CLK0
U2
DQ8-15 DQM0 BA0-1 DQM1
CKE CAS RAS CE WE A0-A12
CLK
CLK0
U3
DQ16-23 DQM0 BA0-1 DQM2
CKE CAS RAS CE WE A0-A12
CLK
CLK0
U4
DQ24-31 DQM0 BA0-1 DQM3
/WE A0 - A12 BA0-1 Vcc
Two 0.01uF Capacitor per each SDRAM
Vss
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PIN FUNCTION DESCRIPTION
Pin CLK /CE Name System clock Chip enable Input Function
HSD32M32M4V
Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge.
/CAS
Column strobe
address
Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active.
/WE
Write enable
DQM0 ~ 3
Data mask
input/output
Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
DQ0 ~ 31 VDD/VSS
Data input/output Power supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG RATING -1V to 4.6V -1V to 4.6V 4W -55oC to 150oC
Short Circuit Output Current IOS 50mA Notes : Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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HSD32M32M4V
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4 UNIT V V V V V 1 2 IOH = -2mA IOL = 2mA 3 NOTE
Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Address(A0~A12, BA0~BA1) /RAS, /CAS, /WE CKE(CKE0) Clock (CLK0) /CE (/CE1) DQM (DQM0 ~ DQM3) DQ (DQ0 ~ DQ32) SYMBOL CADD C IN CCKE CCLK CCS CDQM COUT MIN 15 15 15 7.5 15 6.5 7 MAX 25 25 25 9 25 7.5 8.5 UNITS pF pF pF pF pF pF pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) TEST PARAMETER SYMBOL CONDITION Burst length = 1 Operating current (One bank active) ICC1 tRC tRC(min) IO = 0mA ICC2P CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= 8 mA 8 mA 480 480 440 440 mA 1 -A -8 -H -L VERSION UNIT NOTE
Precharge standby current in power-down mode
ICC2PS
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CKE VIH(min) ICC2N Precharge standby current in one time during 20ns non power-down mode ICC2NS CKE VIH(min) CLK VIL(max), tCC= CS* VIH(min), tCC=10ns
HSD32M32M4V
64 mA
Input signals are changed
56
Input signals are stable Active standby current in ICC3P ICC3PS CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), ICC3N CS*VIH(min), tCC=10ns 120 mA 24 mA 24
power-down mode
Active standby current in non power-down mode (One bank active)
Input signals are changed one time during 20ns CKEVIH(min)
ICC3NS
CLK VIL(max),
tCC=
100
Input signals are stable IO = 0 mA Operating current (Burst mode) ICC4 Page burst 560 4Banks Activated tCCD = 2CLKs Refresh current Self refresh current ICC5 ICC6 tRC tRC(min) CKE 0.2V 840 840 20 8 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). 800 800 mA mA mA 2 G F 560 460 460 mA 1
AC OPERATING TEST CONDITIONS
(vcc = 3.3V 0.3V, TA = 0 to 70C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V ns V
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+3.3V
HSD32M32M4V
Vtt=1.4V 1200
DOUT 870 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA
50 DOUT Z0=50 50pF
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time SYMBOL -A tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max)
tRC(min)
UNIT -8 16 20 20 48 100 65 68 2 2 CLK + 20 ns 1 1 1 2 ea 70 70 -H 20 20 20 50 -L 20 20 20 50 ns ns ns ns ns ns CLK CLK CLK CLK 15 20 20 45
NOTE 1 1 1 1
Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data
1 2.5 5 2 2 3 4
tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 -
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . (Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.)
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AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) -A PARAMETER CLK cycle time CAS 7.5 latency=3 tCC CAS latency=2 CLK to valid output delay CAS 5.4 latency=3 tSAC CAS latency=2 Output data hold time CAS 2.7 latency=3 tOH CAS latency=2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS 5.4 latency=3 tSHZ CAS latency=2 6 6 6 tCH tCL tSS tSH tSLZ 2.5 2.5 1.5 0.8 1 3 3 2 1 1 3 3 2 1 1 3 3 3 6 6 6 10 1000 1000 1000 8 10 SYMBOL MIN MAX MIN MAX MIN MAX -8 -H
HSD32M32M4V
-L UNIT MIN 10 1000 12 ns 1 MAX NOTE
6 ns 7 1,2
3 ns 3 3 3 2 1 1 6 ns ns ns ns ns ns 3 3 3 3 3 2 2
7
ns
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter.
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode register set Auto refresh Refresh Self refres h Entry Exit CKE n-1 H H L H CKE n X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1 A10/ AP OP code X X Row address
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A11,A12, A9~A0
NOTE 1,2 3 3 3 3
Bank active & row addr.
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Auto disable Auto disable Auto disable Auto disable Burst Stop Precharg e Bank selection All banks Entry Exit Entry Exit H H H L H L H H X H L X X L H L H L L H L X H L H L L L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X V X precharge precharge H X L H L L X V precharge precharge H X L H L H X V
HSD32M32M4V
Read & column address
L H
Column Address (A0 ~ A9) Column
4 4,5
Write & column address
L
Address (A0 ~ A9)
4
H X L H X X
4,5 6
Clock suspend or active power down
Precharge down mode DQM
power
X X V X X X 7
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TIMING DIAGRAMS
Please refer to timing diagram chart (II)
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HSD32M32M4V
PACKAGING INFORMATION
Unit : mm
107.95 20 17.8 0.2 3.38 3.2
10.16 6.35 2.03
44.45
1.27
1.00
95.25 6.35 6.35
0.25 MAX
2.54 MIN 1.270.08 Gold: 1.040.10 1.27 Solder: 0.9140.10
(Solder & Gold Plating)
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ODERING INFORMATION
HSD32M32M4V
Part Number
Density
Org.
Package 72 Pin SIMM 72 Pin SIMM 72 Pin SMM 72 Pin SIMM 72 Pin SIMM 72 Pin SIMM 72 Pin SIMM 72 Pin SIMM
Ref.
Vcc
Feature
MAX.frq 133MHz (CL=3)
HSD32M32M4V-13 HSD32M32M4V-F13 HSD32M32M4V-12 HSD32M32M4V-F12 HSD32M32M4V-10 HSD32M32M4V-F10 HSD32M32M4V-10L HSD32M32M4V-F10L
128MByte 128MByte 128MByte 128MByte 128MByte 128MByte 128MByte 128MByte
32Mx 32 32Mx 32 32Mx 32 32Mx 32 32Mx 32 32Mx 32 32Mx 32 32Mx 32
8K 8K 8K 8K 8K 8K 8K 8K
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Low Power Low Power Low Power Low Power
133MHz (CL=3) 125MHz (CL=3) 125MHz (CL=3) 100MHz (CL=2) 100MHz (CL=2) 100MHz 100MHz
F means Auto & Self refresh with Low - Power (3.3V)
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